The invention relates generally to electronic communications hardware and deals more particularly with a technique to detect the end of a serial bit stream which does not include an explicit end of bit stream signal.
There are many applications where serial data is transmitted from a source to a destination. For example, digital data may be sent serially from a television transmission station to a data converter in a subscriber's home via a satellite in a compressed format. The data converter receives the serial data and then converts it to parallel format for processing by digital decompression hardware. The data converter needs to determine when the serial bit stream has ended; otherwise the data converter could interpret the subsequent lull as a series of data bits of constant level. Some communication protocols require an explicit end of bit stream signal or "footer", and the data converter merely senses that signal to determine when the serial bit stream has ended. However, when the data is sent according to a standard defined by IEEE High Performance Serial Bus Specification 1394, there is no explicit signal identifying the end of the serial bit stream. Rather, the serial bit stream merely ends after the last of the normal data bits.
The problem is further complicated in data converters which are operated asynchronously relative to the serial bit stream which is received, i.e. the received serial bit stream is based on a clock of the source whereas the data converter generates and uses its own clock to determine the end of the serial bit stream (and perform the serial to parallel conversion and decompression).
Accordingly, a general object of the present invention is to provide circuitry and a method to detect the end of a serial bit stream which does not include an explicit end of bit stream signal.
A more specific object of the present invention is to provide a detector of the foregoing type which operates on a serial bit stream which is asynchronous relative to a clock within the detector.